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(R)
LY61L256
Rev. 1.2
32K X 8 BIT HIGH SPEED CMOS SRAM
REVISION HISTORY
Revision Rev. 1.0 Rev. 1.1 Description Initial Issue Revised VTERM to VT1 and VT2 Revised Test Condition of ISB1/IDR Added LL Spec. Revised Test Condition of ICC/ISB Revised FEATURES & ORDERING INFORMATION Lead free and green package available to Green package available Deleted TSOLDER in ABSOLUTE MAXIMUN RATINGS Added packing type in ORDERING INFORMATION Issue Date Jul.25.2004 Feb.2.2009
Rev. 1.2
Apr.17.2009
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 0
(R)
LY61L256
Rev. 1.2
32K X 8 BIT HIGH SPEED CMOS SRAM
GENERAL DESCRIPTION
The LY61L256 is a 262,144-bit high speed CMOS static random access memory organized as 32,768 words by 8 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The LY61L256 is well designed for high speed system application. Easy expansion is provided by using an active LOW Chip Enable(CE#). The active LOW Write Enable(WE#) controls both writing and reading of the memory. The LY61L256 operates from a single power supply of 3.3V and all inputs and outputs are fully TTL compatible
FEATURES
Fast access time : 10/12/15ns Low power consumption: Operating current : 60/50/40mA (TYP.) Standby current : 0.5mA (TYP.) 1A (TYP.) LL-version Single 3.3V power supply All inputs and outputs TTL compatible Fully static operation Tri-state output Data retention voltage : 2.0V (MIN.) Green package available Package : 28-pin 300 mil SOJ 28-pin 8mm x 13.4mm STSOP
PRODUCT FAMILY
Product Family LY61L256 LY61L256 LY61L256(E) LY61L256(E) LY61L256(I) LY61L256(I) LY61L256(LL) LY61L256(LL) LY61L256(LLE) LY61L256(LLE) LY61L256(LLI) LY61L256(LLI) Operating Temperature 0 ~ 70 0 ~ 70 -20 ~ 80 -20 ~ 80 -40 ~ 85 -40 ~ 85 0 ~ 70 0 ~ 70 -20 ~ 80 -20 ~ 80 -40 ~ 85 -40 ~ 85 Vcc Range 3.15 ~ 3.6V 3.0 ~ 3.6V 3.15 ~ 3.6V 3.0 ~ 3.6V 3.15 ~ 3.6V 3.0 ~ 3.6V 3.15 ~ 3.6V 3.0 ~ 3.6V 3.15 ~ 3.6V 3.0 ~ 3.6V 3.15 ~ 3.6V 3.0 ~ 3.6V Speed 10ns 12/15ns 10ns 12/15ns 10ns 12/15ns 10ns 12/15ns 10ns 12/15ns 10ns 12/15ns Power Dissipation Standby(ISB1,TYP.) Operating(Icc,TYP.) 0.5mA 60mA 0.5mA 50/40mA 0.5mA 60mA 0.5mA 50/40mA 0.5mA 60mA 0.5mA 50/40mA 60mA 1A(LL) 50/40mA 1A(LL) 60mA 1A(LL) 50/40mA 1A(LL) 60mA 1A(LL) 50/40mA 1A(LL)
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 1
(R)
LY61L256
Rev. 1.2
32K X 8 BIT HIGH SPEED CMOS SRAM
PIN DESCRIPTION
SYMBOL A0 - A14
DECODER 32Kx8 MEMORY ARRAY
FUNCTIONAL BLOCK DIAGRAM
Vcc Vss
DESCRIPTION Address Inputs Data Inputs/Outputs Chip Enable Input Write Enable Input Output Enable Input Power Supply Ground
DQ0 - DQ7 CE# WE# OE# VCC VSS
A0-A14
DQ0-DQ7
I/O DATA CIRCUIT
COLUMN I/O
CE# WE# OE#
CONTROL CIRCUIT
PIN CONFIGURATION
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SOJ 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vcc WE# A13 A8 A9 A11 OE# A10 CE# I/O8 I/O7 I/O6 I/O5 I/O4 OE# A11 A9 A8 A13 WE# Vcc A14 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 CE# I/O8 I/O7 I/O6 I/O5 I/O4 Vss I/O3 I/O2 I/O1 A0 A1 A2
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 2
LY61L256
LY61L256
STSOP
(R)
LY61L256
Rev. 1.2
32K X 8 BIT HIGH SPEED CMOS SRAM
ABSOLUTE MAXIMUN RATINGS*
PARAMETER Voltage on VCC relative to VSS Voltage on any other pin relative to VSS Operating Temperature Storage Temperature Power Dissipation DC Output Current SYMBOL VT1 VT2 TA TSTG PD IOUT RATING -0.5 to 4.6 -0.5 to VCC+0.5 0 to 70(C grade) -20 to 80(E grade) -40 to 85(I grade) -65 to 150 1 50 UNIT V V W mA
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE Standby Output Disable Read Write
Note:
CE# H L L L
OE# X H L X
WE# X H H L
I/O OPERATION High-Z High-Z DOUT DIN
SUPPLY CURRENT ISB,ISB1 ICC,ICC1 ICC,ICC1 ICC,ICC1
H = VIH, L = VIL, X = Don't care.
DC ELECTRICAL CHARACTERISTICS
PARAMETER Supply Voltage Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage SYMBOL VCC VIH *2 VIL ILI ILO VOH VOL ICC Average Operating Power supply Current ICC1 ISB Standby Power Supply Current ISB1
*1
TEST CONDITION -10 -12/-15
VCC VIN VSS VCC VOUT VSS, Output Disabled IOH = -4mA IOL = 8mA -10 Cycle time = Min. CE# = VIL , II/O = 0mA -12 Others at VIL or VIH -15 Cycle time = 1s CE#0.2V and II/O = 0mA Other pins at 0.2V or VCC-0.2V CE# = VIH, others at VIL or VIH CE# VCC - 0.2V Normal CE# VCC - 0.2V LL Others at 0.2V or VCC-0.2V
MIN. 3.15 3.0 2.0 - 0.5 -1 -1 2.4 -
TYP. 3.3 3.3 3.0 60 50 40 1 10 0.5 1
*4
MAX. 3.6 3.6 VCC+0.5 0.6 1 1 0.4 75 60 50 5 15 3 20
UNIT V V V V A A V V mA mA mA mA mA mA A
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 3
(R)
LY61L256
Rev. 1.2
32K X 8 BIT HIGH SPEED CMOS SRAM
Notes: 1. VIH(max) = VCC + 3.0V for pulse width less than 10ns. 2. VIL(min) = VSS - 3.0V for pulse width less than 10ns. 3. Over/Undershoot specifications are characterized, not 100% tested. 4. Typical values are included for reference only and are not guaranteed or tested. Typical valued are measured at VCC = VCC(TYP.) and TA = 25
CAPACITANCE (TA = 25, f = 1.0MHz)
PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN.
-
MAX 6 8
UNIT pF pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0.2V to VCC - 0.2V 3ns 1.5V CL = 30pF + 1TTL, IOH/IOL = -4mA/8mA
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low-Z Output Enable to Output in Low-Z Chip Disable to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High-Z SYM. tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH LY61L256-10 MIN. MAX. 10 10 10 5 2 0 5 5 1 LY61L256-12 MIN. MAX. 12 12 12 6 3 0 6 6 3 LY61L256-15 MIN. MAX. 15 15 15 7 4 0 7 7 3 UNIT ns ns ns ns ns ns ns ns ns
SYM. tWC tAW tCW tAS tWP tWR tDW tDH tOW* tWHZ*
LY61L256-10 MIN. MAX. 10 8 8 0 8 0 6 0 2 6
LY61L256-12 MIN. MAX. 12 10 10 0 9 0 7 0 3 7
LY61L256-15 MIN. MAX. 15 12 12 0 10 0 8 0 4 8
UNIT ns ns ns ns ns ns ns ns ns ns
*These parameters are guaranteed by device characterization, but not production tested.
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 4
(R)
LY61L256
Rev. 1.2
32K X 8 BIT HIGH SPEED CMOS SRAM
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2)
tRC Address tAA Dout Previous Data Valid tOH Data Valid
READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5)
tRC Address tAA CE# tACE OE# tOE tOLZ tCLZ Dout High-Z tOH tOHZ tCHZ Data Valid High-Z
Notes : 1.WE# is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low. 3.Address must be valid prior to or coincident with CE# = low,; otherwise tAA is the limiting parameter. 4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured 500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ.
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 5
(R)
LY61L256
Rev. 1.2
32K X 8 BIT HIGH SPEED CMOS SRAM
WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)
tWC Address tAW CE# tCW tAS WE# tWHZ Dout (4) High-Z tDW Din tDH TOW (4) tWP tWR
Data Valid
WRITE CYCLE 2 (CE# Controlled) (1,2,5,6)
tWC Address tAW CE# tAS tCW tWP WE# tWHZ Dout (4) High-Z tDW Din tDH tWR
Data Valid
Notes : 1.WE#, CE# must be high during all address transitions. 2.A write occurs during the overlap of a low CE#, low WE#. 3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured 500mV from steady state.
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 6
(R)
LY61L256
Rev. 1.2
32K X 8 BIT HIGH SPEED CMOS SRAM
DATA RETENTION CHARACTERISTICS
PARAMETER VCC for Data Retention SYMBOL TEST CONDITION VDR CE# VCC - 0.2V VCC = 2.0V Normal CE# VCC - 0.2V IDR VCC = 2.0V CE# VCC - 0.2V LL Others at 0.2V or VCC-0.2V See Data Retention tCDR Waveforms (below) tR MIN. 2.0 0 tRC* TYP. 0.3 0.5 MAX. 3.6 2 20 UNIT V mA A ns ns
Data Retention Current
Chip Disable to Data Retention Time Recovery Time tRC* = Read Cycle Time
DATA RETENTION WAVEFORM
VDR 2.0V Vcc Vcc(min.) tCDR CE# VIH CE# Vcc-0.2V Vcc(min.) tR VIH
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 7
(R)
LY61L256
Rev. 1.2
32K X 8 BIT HIGH SPEED CMOS SRAM
PACKAGE OUTLINE DIMENSION
28-pin 300 mil SOJ Package Outline Dimension
28
15
1
14
A2
C L
X XX
UNIT SYM.
INCH(REF)
MM(BASE)
A 0.140 (MAX) 3.556 (MAX) A1 0.026 (MIN) 0.660 (MIN) A2 0.1000.005 2.5400.127 B 0.0180.003 0.4570.076 B1 0.028 0.003 0.7110.076 c 0.0100.003 0.2540.076 D 0.7100.010 18.030.254 E 0.3370.010 8.5600.254 E1 0.3000.005 7.6200.127 e 0.0500.003 1.2700.076 L 0.0870.010 2.2100.254 S 0.0300.004 0.7620.102 Y 0.003 (MAX) 0.076 (MAX) Note : 1.S/E/D dimension is not including mold flash. 2.The end flash in package lengthwise is not more than 10 mils each side. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 8
(R)
LY61L256
Rev. 1.2
32K X 8 BIT HIGH SPEED CMOS SRAM
28 pin 8x13.4mm STSOP Package Outline Dimension
HD
c L
12 (2x)
1 28
12 (2x)
e
14 15
"A"
D Seating Plane
b
E
y
12 (2X)
14
15
GAUGE PLANE A A2 c 0.254 0 A1 SEATING PLANE 12 (2X) L
1 28
"A" DATAIL VIEW
L1
SYMBOLS A A1 A2 b c HD D E e L L1 Y
DIMENSIONS IN MILLIMETERS MIN NOM MAX 1.00 1.10 1.20 0.05 0.15 0.91 1.00 1.05 0.17 0.22 0.27 0.10 0.15 0.20 13.20 13.40 13.60 11.70 11.80 11.90 7.90 8.00 8.10 0.55 0.30 0.50 0.70 0.675 0.00 0.076 0 3 5
DIMENSIONS IN INCHES MIN NOM MAX 0.040 0.043 0.047 0.002 0.006 0.036 0.039 0.041 0.007 0.009 0.011 0.004 0.006 0.008 0.520 0.528 0.535 0.461 0.465 0.469 0.311 0.315 0.319 0.0216 0.012 0.020 0.028 0.027 0.000 0.003 0 3 5
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 9
(R)
LY61L256
Rev. 1.2
32K X 8 BIT HIGH SPEED CMOS SRAM
ORDERING INFORMATION
LY61L256 U V - WW XX Y Z
Z : Packing Type Blank : Tube or Tray T : Tape Reel Y : Temperature Range Blank : (Commercial) 0C ~ 70C E : (Extended) -20C ~ +80C I : (Industrial) -40C ~ +85C XX : Power Type LL : Ultra Low Power WW : Access Time(Speed) V : Lead Information L : Green Package U : Package Type J : 28-pin 300 mil SOJ R : 28-pin 8 mm x 13.4 mm STSOP
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 10
(R)
LY61L256
Rev. 1.2
32K X 8 BIT HIGH SPEED CMOS SRAM
THIS PAGE IS LEFT BLANK INTENTIONALLY.
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 11

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